Some types of field effect transistors (FETs) have three-dimensional, non-planar configurations including fin-like structures extending above substrates. Such field effect transistors are referred to as FinFETs. The substrates may include semiconductor on insulator (SOI) substrates or bulk semiconductor substrates. Silicon fins are formed in some FinFETs on substrates via known technology such as sidewall image transfer (SIT). FinFET structures including SOI substrates can be formed, in part, by selectively etching the crystalline silicon layers down to the oxide or other insulating layers thereof following photolithography. Active fin heights are set by SOI thickness when employing SOI substrates. In bulk FinFETs, active fin height is set by oxide thickness and etched fin height. The gates of FinFETs can be formed using a “gate-first” process wherein a gate stack and spacers are formed prior to selective epitaxial growth wherein source and drain regions are enlarged. A “gate-last” process may alternatively be employed wherein the source/drain regions are formed immediately following fin patterning. Gate-last procedures can involve making a dummy gate, fabricating other elements of the transistor, removing the dummy gate, and replacing the removed dummy gate with actual gate materials.
Doped semiconductor material may be provided by selective epitaxial growth on the sidewalls of the fin structure(s) during fabrication of FinFETs. Such growth results in faceted structures that, in some cases, merge into a continuous volume. Annealing during the fabrication of FinFETs can cause dopants to diffuse into regions where such dopants are not desired.
Silicon germanium fins are employed in some p-type FinFET devices. Fabrication of silicon germanium fins may include growing a layer of silicon germanium on a silicon substrate and cutting fins from the silicon germanium layer. Fins are also cut from an adjoining silicon layer to form an nFET region. To isolate the silicon germanium fins, a well implant is provided to create an oppositely doped sub-layer that functions as a punch through stop (PTS).
A p-well 22 and an n-well 24 are formed by ion implantation of boron and arsenic, respectively, within a silicon substrate 26. If a structure including both silicon and silicon germanium fins is to be fabricated, a recess is formed in the pFET region of the structure followed by deposition of a silicon germanium layer 28. The structure 50 shown in FIG. 5 is thereby obtained. Using known techniques for cutting fins, such as photolithography or sidewall image transfer, silicon fins 32 are formed in the nFET region and silicon germanium fins 34 are formed in the pFET region, as shown in FIG. 6. Subsequent thermal processing of the structure 60 shown in FIG. 6, as employed using conventional CMOS fabrication techniques, includes annealing. As shown in FIG. 7, dopants 24A (e.g. arsenic) from the n-well diffuse up the silicon germanium fins and contaminate the pFET region. This is less of a problem if silicon fins are used in the pFET region as arsenic does not diffuse as fast in silicon as it does in silicon germanium. Phosphorus, another n-type dopant having a higher diffusion coefficient than arsenic, would contaminate the pFET region even more than arsenic. An oxide layer 29 is formed on the substrate 26 to provide electrical isolation.